Double data rate synchronous dynamic random-access memory (DDR SDRAM) modules are commonly used in high speed memory systems. In DDR memory systems, data is transferred on both the rising and falling edges of the clock signal to achieve approximately twice the bandwidth as compared to a single data rate random-access memory (SDR SDRAM) running at the same clock frequency.
High speed output buffer circuits are commonly used in integrated circuits employing high speed DDR memory systems to provide an output signal to the DDR memory module that is a function of a data input signal from other logic circuitry of the integrated circuit.
With reference to FIG. 1, the output driver 10 of a buffer circuit utilized in a DDR memory module typically utilizes a pull-up transistor 15 and a pull-down transistor 20 connected in series between an internal power supply potential node (VDD) 25 and a ground potential node (GND) 30. The common node 35 between the pull-up transistor 15 and the pull-down transistor 20 is further connected to an output terminal. The output load at the output terminal may be modeled as a resistor RL 40 coupled to output signal node (VTT=(1/2)*VDD) 45, which is commonly used in a DDR system. The output signal 35 at the output terminal 35 is used to drive additional circuitry of the integrated circuit device.
As is commonly known in the art, the driver may consist of complimentary logic transistors, wherein the pull-up transistor 15 may be a PMOS transistor and the pull-down transistor 20 may be an NMOS transistor. In a typical driver 10, the gate of the pull-up transistor 15 and the pull-down transistor 20 are both coupled to the data input or control signal 50. In this configuration, depending upon the logic state of the data input signal (In) 50 to the output buffer circuit 10, either the pull-up transistor 15 or the pull-down transistor 20 is quickly turned ON while the other is turned OFF. In an exemplary embodiment, when the input signal 50 is 0, the transistor Mn 20 is OFF and transistor Mp 15 is ON. When transistor Mp 15 is ON, the driver 10 sources current from VDD 25, Mp 15 and Rp 55 to the output node 35. When the input signal is 1, the transistor Mp 15 is OFF and transistor Mn 20 is ON. When transistor Mn 20 is ON, the driver 10 sinks current from output node 35, Mn 20 and Rn 60 to GND 30.
In a high speed driver 10, such as that used in a DDR system, the data frequency rate is high and therefore the transistors Mp 15 and Mn 20 are rapidly switching ON and OFF. During the rapid ON and OFF of the pull-up transistor 15 and the pull-down transistor 20, there exists a condition in which the pull-up transistor 15 remains ON temporarily as it is being turned OFF, while at the same time, the pull-down transistor 20 is being turned ON. This condition causes a sudden surge of current to flow through the pull-up transistor 15 and the pull-down transistor 20 of the driver 10 from VDD 20 to GND 30. The current generated through the driver when both transistors are temporarily in the ON state is commonly referred to as a crowbar current. The crowbar current is undesirable because it increases the overall power consumption of the driver 10.
In addition to minimizing the crowbar current of the driver 10, it is also desirable to control the output buffer's switching speed, or slew rate. The slew rate of the output driver 10 is equal to the change in output voltage 45 of the driver over time. In a DDR system, it is desirable for the output driver 10 to generate an output signal 45 having a slew rate within a reasonable range to drive the next stage DRAM while still being low enough to minimize reflections and electromagnetic interference (EMI).
Accordingly, what is needed in the art is an output driver having a reduced crowbar current and a controllable slew rate.